The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to an improvement in an isolation technique for manufacturing an IC or LSI.
Generally, p-n junction isolation or selective oxidation has been used as an isolation technique for manufacturing a semiconductor device, particularly, a bipolar IC or MOSIC. However, such an isolation technique has various drawbacks. For example, according to the p-n junction isolation method, lateral diffusion of an impurity in an isolating diffusion region is great, so that the packing density of the semiconductor device is decreased. According to the selective oxidation method, mechanical stress due to extension of an oxide film into the element region at the end of the field region is increased to cause crystal defects, and a dimensional change is increased due to the extension of the oxide film. Therefore, neither the p-n junction isolation method nor the selective oxidation method is suitable to manufacture a highly integrated LSI.
Various studies have been made recently in consideration of the above problems, and a number of new isolation techniques have been proposed. For example, an isolation method is described in "Int. Electron Devices Meeting Dig. Tech. Paper", PP. 384 to 387, 1981. This method comprises the steps of forming a groove which has a desired depth by etching a silicon layer of a perspective wide isolating region, depositing a silicon oxide film as an isolating material to cover the entire surface, leaving an isolating material film in the wide groove by selectively etching by the lift-off method a portion of the silicon oxide film which corresponds to a prospective element formation region, depositing another silicon oxide film on the entire surface, and back-etching the silicon oxide film to expose the surface portion of the semiconductor layer which corresponds to the prospective isolation formation region so as to bury the narrow groove between the isolating material film and the portion of the semiconductor layer which corresponds to the prospective element formation region.
According to the above method, it is possible to principle to leave the isolating film (field film) in the wide and narrow process of the same depth. In the semiconductor device such as a bipolar IC or a CMOS transistor, a narrow but deep isolating region may often be required in addition to the shallow isolating region. For example, when a narrow but deep insulating material isolation region is formed in place of the p-n junction isolation region of the bipolar element, or the narrow but deep insulating material is formed to provide a channel cut in the vicinity of the well region of the CMOS element or to prevent the latch-up phenomenon, the performance of the semiconductor element is greatly improved. Furthermore, micronization of the element can be achieved. However, according to the method described above, such a narrow but deep insulating material isolation layer can hardly be formed.